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Automatic RF MESFET Amplifier
Drain-Current Controllers
The ADCBUSY bit, D3, is set to 1 when the ADC is
busy, an ALARM value is being checked, or the ADC
results are being loaded into the FIFO. ADCBUSY
returns to 0 after the ADC completes all of the conver-
sions in the current scan. The VGBUSY bit, D2, is set to
1 when the ALU is performing a lookup and interpola-
tion or V DAC(CODE) calculation for either channel. The
FIFOEMP bit, D1, is set to 1 when the FIFO is empty
and contains no data. FIFOEMP is reset to 0 if data is
written into the FIFO. Writing to the software clear regis-
ter with FIFOCLR set to 1 causes the FIFO to be
cleared, which then sets FIFOEMP to 1.
The functionality of the FIFOOVR bit, D0, depends on
whether the FIFO is loaded with ADC data or LUT data.
FIFOOVR functions in one of two modes:
1) Reading the ADC data: FIFOOVR is set to 1 if the
FIFO has a data overflow. FIFOOVR is reset to 0
only by reading the flag register or by clearing the
FIFO through the software clear register. Emptying
the FIFO does not clear the FIFOOVR bit.
2) Reading the LUT data: When commanding a LUT
read, the FIFO is no longer allowed to overflow.
FIFOOVR is set to 1 if the LUT is full and set to 0 if
the LUT is not full, for that instant in time only. See
the FIFO Description section.
ALMFLAG (Read)
Read the ALARM flag register to determine the source of
an ALARM condition. Set the command byte to F8h to
read the ALARM flag register. Bits D15–D12 are don’t
care. See Table 27. Bits D11–D0 are all reset to 0 follow-
ing a read of the ALARM flag register or a software clear
command. The HIGH-V2 bit, D11, is set to 1 when the
GATE2 voltage exceeds the high threshold setting. The
LOW-V2 bit, D10, is set to 1 when the GATE2 voltage
decreases below the low threshold setting. The HIGH-I2
bit, D9, is set to 1 when the channel 2 sense voltage
exceeds the high threshold setting. The LOW-I2 bit, D8,
is set to 1 when the channel 2 sense voltage decreases
below the low threshold setting. The HIGH-T2 bit, D7, is
set to 1 when the channel 2 external temperature
exceeds the high threshold setting. The LOW-T2 bit, D6,
is set to a 1 when the channel 2 external temperature
decreases below the low threshold setting.
The HIGH-V1 bit, D5, is set to 1 when the GATE1 volt-
age exceeds the high threshold setting. The LOW-V1
bit, D4, is set to 1 when the GATE1 voltage decreases
below the low threshold setting. The HIGH-I1 bit, D3, is
set to 1 when the channel 1 sense voltage exceeds the
high threshold setting. The LOW-I1 bit, D2, is set to 1
when the channel 1 sense voltage decreases below the
low threshold setting. The HIGH-T1 bit, D1, is set to 1
when the channel 1 external temperature exceeds the
high threshold setting. The LOW-T1 bit, D0, is set to a 1
when the channel 1 external temperature decreases
below the low threshold setting.
FIFO Description
The MAX11014/MAX11015’s FIFO stores 15 ADC sam-
ples or 16 SRAM LUT data words. Read the FIFO to
load the FIFO data onto DOUT in SPI mode and SDA in
I 2 C mode. See Table 25. The ADC sample data
includes a 4-bit channel tag, followed by 12 bits of
data. The ADC channel tags indicate the source for the
temperature or voltage result. The LUT data includes a
3-bit channel tag for LUT configuration word data and a
4-bit tag for all other LUT data. The LUT tags indicate
whether the LUT data is temperature (T) or numerical
(K)-based. Do not mix ADC results with LUT results in
the FIFO.
The FIFO allows overflows of ADC data and it always
contains the 15 most recent ADC conversion results.
Read the FIFO quickly enough to prevent an overflow
condition. Detect if the FIFO has overflowed (indicating
a loss of data) by inspecting the FIFOOVR bit in the flag
register.
The FIFO does not overflow while outputting SRAM LUT
data. Count how many words are output in order
(through the numerical representation of the LUTWORD
bits in the LUT address register) to tell which LUT data
word is being supplied.
ADC Monitoring Mode
Each time the ADC converts a sample in ADC monitor-
ing mode, the data word and its 4-bit channel tag are
moved into the FIFO. Load the data from the FIFO to
DOUT in SPI mode and SDA in I 2 C mode by writing
command byte 80h.
The hardware configuration register ’s ADCMON bit
determines whether ADC samples are loaded into the
FIFO. See Table 10. Set ADCMON to 1 to store ADC
samples in the FIFO. Set to 0 to not load ADC results
into the FIFO. The value of ADCMON does not affect
whether the results from any particular ADC conversion
are checked against the ALARM thresholds or exam-
ined for changes to the V DAC(CODE) equations.
After reading out all of the ADC FIFO data, the flag regis-
ter sets the FIFOEMP bit to 1. If a FIFO read command is
issued with the FIFO empty, the FIFO returns a channel
tag of 1111 and the 12 flag register bits. See Table 25.
The FIFO allows interface reads to be simultaneous with
the arrival of new ADC sample or LUT data words. But
when the FIFO is full and overflowing, if an ADC sample
arrives at exactly the same time as an interface read,
there is a possibility of data corruption. This condition is
52
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